CY2291
Three-PLL General Purpose EPROM
Programmable Clock Generator
Features
Benefits
■ Three integrated phase-locked loops
■ EPROM programmability
■ Generates up to three custom frequencies from external
sources
■ Easy customization and fast turnaround
■ Factory-programmable (CY2291) or field-programmable
(CY2291F) device options
■ Programming support available for all opportunities
■ Meets critical industry standard timing requirements
■ Supports low-power applications
■ Low-skew, low-jitter, high-accuracy outputs
■ Power-management options (Shutdown, OE, Suspend)
■ Frequency select option
■ Eight user-selectable frequencies on CPU PLL
■ Allows downstream PLLs to stay locked on CPUCLK output
■ Enables application compatibility
■ Smooth slewing on CPUCLK
■ Configurable 3.3V or 5V operation
■ 20-pin SOIC Package
■ Industry-standard packaging saves on board space
Part Number Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY2291
CY2291I
CY2291F
CY2291FI
8
8
8
8
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
76.923 kHz–100 MHz (5V)
76.923 kHz–80 MHz (3.3V)
Factory Programmable
Commercial Temperature
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
76.923 kHz–90 MHz (5V)
76.923 kHz–66.6 MHz (3.3V)
Factory Programmable
Industrial Temperature
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
76.923 kHz–90 MHz (5V)
76.923 kHz–66.6 MHz (3.3V)
Field Programmable
Commercial Temperature
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
76.923 kHz–80 MHz (5V)
76.923 kHz–60.0 MHz (3.3V)
Field Programmable
Industrial Temperature
Logic Block Diagram
32XIN
32XOUT
XTALIN
32K
OSC.
OSC.
XBUF
CPUCLK
CLKA
XTALOUT
CPLL
(8 BIT)
/1,2,4
S0
S1
S2/SUSPEND
UPLL
(10 BIT)
CLKB
/1,2,4,8
CLKC
CLKD
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96,104
SPLL
(8 BIT)
/2,3,4
CLKF
CONFIG
EPROM
SHUTDOWN/
OE
Cypress Semiconductor Corporation
Document #: 38-07189 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 16, 2008
CY2291
combination. The only limitation is that if a PLL is shut off, all
outputs derived from it must also be shut off. Suspending a PLL
Operation
The CY2291 is a third-generation family of clock generators. The
CY2291 is upwardly compatible with the industry standard
ICD2023 and ICD2028 and continues their tradition by providing
a high level of customizable features to meet the diverse clock
generation needs of modern motherboards and other
synchronous systems.
forces a three-state condition.
The CPUCLK can slew (transition) smoothly between 8 MHz and
the maximum output frequency (100 MHz at 5V/80 MHz at 3.3V
for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz at 3.3V
for Industrial Temp. and for field-programmed parts). This feature
is extremely useful in “Green” PC and laptop applications, where
reducing the frequency of operation can result in considerable
power savings. This feature meets all 486 and Pentium®
processor slewing requirements.
All parts provide a highly configurable set of clocks for PC
motherboard applications. Each of the four configurable clock
outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in
any combination. Multiple outputs configured for the same or
related[3] frequencies have low (<500 ps) skew, in effect
providing on-chip buffering for heavily loaded signals.
CyClocks Software
The CY2291 can be configured for either 5V or 3.3V operation.
The internal ROM tables use EPROM technology, allowing full
customization of output frequencies. The reference oscillator has
been designed for 10 MHz to 25 MHz crystals, providing
additional flexibility. No external components are required with
this crystal. Alternatively, an external reference clock of
frequency between 1 MHz and 30 MHz can be used. Customers
using the 32-kHz oscillator must connect a 10-MW resistor in
parallel with the 32-kHz crystal.
CyClocks™ is an easy-to-use application that allows you to
configure any one of the EPROM programmable clocks offered
by Cypress. You may specify the input frequency, PLL and output
frequencies, and different functional options. Please note the
output frequency ranges in this data sheet when specifying them
in CyClocks to ensure that you stay within the limits. CyClocks
also has a power calculation feature that allows you to see the
power consumption of your specific configuration. CyClocks is a
sub-application within the CyberClocks™ software. You can
download a copy of CyberClocks for free on Cypress’s web site
Output Configuration
The CY2291 has five independent frequency sources on-chip.
These are the 32-kHz oscillator, the reference oscillator, and
three Phase-Locked Loops (PLLs). Each PLL has a specific
function. The System PLL (SPLL) drives the CLKF output and
provides fixed output frequencies on the configurable outputs.
The SPLL offers the most output frequency divider options. The
CPU PLL (CPLL) is controlled by the select inputs (S0–S2) to
provide eight user-selectable frequencies with smooth slewing
between frequencies. The Utility PLL (UPLL) provides the most
accurate clock. It is often used for miscellaneous frequencies not
provided by the other frequency sources.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Programmers
is a portable programmer designed to custom program our family
of EPROM Field Programmable Clock Devices. The FTG
programmers connect to a PC serial port and allow users of
CyClocks software to quickly and easily program any of the
CY2291F, CY2292F, CY2071AF, and CY2907F devices. The
ordering code for the Cypress FTG Programmer is CY3670.
Custom Configuration Request Procedure
All configurations are EPROM programmable, providing short
sample and production lead times. Please refer to the application
note “Understanding the CY2291, CY2292, and CY2295” for
information on configuring the part.
The CY229x are EPROM-programmable devices that may be
configured in the factory or in the field by a Cypress Field Appli-
cation Engineer (FAE). The output frequencies requested are
matched as closely as the internal PLL divider and multiplier
options allow. All custom requests must be submitted to your
local Cypress FAE or sales representative. The method to use to
request custom configurations is:
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when pulled
LOW (the 32-kHz clock output is not affected). If system
shutdown is enabled, a LOW on this pin also shuts off the PLLs,
counters, the reference oscillator, and all other active compo-
Use CyClocks™ software. This software automatically calcu-
lates the output frequencies that can be generated by the
CY229x devices and provides a print-out of final pinout which
can be submitted (in electronic or print format) to your local FAE
or sales representative. The CyClocks software is available free
from your local sales representative.
nents. The resulting current on the V pins are less than 50 μA
DD
(for Commercial Temp. or 100 μA for Industrial Temp.) plus 15
μA max. for the 32-kHz subsystem and is typically 10 μA. After
leaving shutdown mode, the PLLs have to re-lock. All outputs
Once the custom request has been processed you receive a part
number with a 3-digit extension (for example, CY2292SC-128)
specific to the frequencies and pinout of your device. This is the
part number used for samples requests and production orders.
when three-stated.
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs except 32K can be shut off in nearly any
Document #: 38-07189 Rev. *C
Page 3 of 12
CY2291
Maximum Ratings
(Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.)
Max. Soldering Temperature (10 sec) ......................... 260°C
Junction Temperature.................................................. 150°C
Package Power Dissipation...................................... 750 mW
Supply Voltage...............................................–0.5V to + 7.0V
DC Input Voltage ...........................................–0.5V to + 7.0V
Storage Temperature ................................. –65°C to +150°C
Static Discharge Voltage.............................................≥ 2000V
(per MIL-STD-883, Method 3015)
Parameter
Description
Part Numbers
Min.
4.5
3.0
2.0
0
Max.
5.5
3.6
5.5
+70
+85
25
Unit
V
V
Supply Voltage, 5.0V operation
All
All
All
DD
V
V
Supply Voltage, 3.3V operation
V
DD
Battery Backup Voltage
V
BATT
T
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
Max. Load Capacitance 5.0V Operation
Max. Load Capacitance 3.3V Operation
External Reference Crystal
CY2291/CY2291F
°C
A
CY2291I/CY2291FI
−40
°C
C
All
All
All
All
pF
pF
MHz
MHz
ms
LOAD
C
15
LOAD
f
10.0
1
25.0
30
REF
External Reference Clock
t
Power up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic)
0.05
50
PU
Electrical Characteristics, Commercial 5.0V
Parameter
Description
HIGH-Level Output Voltage I = 4.0 mA
Conditions
Min.
2.4
Typ.
Max.
Unit
V
V
OH
OH
V
V
LOW-Level Output Voltage
I
I
= 4.0 mA
= 0.5 mA
0.4
0.4
V
OL
OL
32.768-kHz HIGH-Level
Output Voltage
V
0.5
V
OH–32
OH
BATT
V
32.768-kHz LOW-Level
Output Voltage
I
= 0.5 mA
V
OL–32
OL
V
V
I
Except crystal pins
Except crystal pins
2.0
V
V
HIGH-Level Input Voltage
IH
0.8
10
LOW-Level Input Voltage
Input HIGH Current
IL
V
V
= V – 0.5V
<1
<1
μA
μA
μA
mA
IH
IN
DD
I
I
I
Input LOW Current
= +0.5V
10
IL
IN
Output Leakage Current
Three-state outputs
250
100
OZ
DD
V
Supply Current
V
= V Max., 5V operation
75
10
5
DD
DD
DD
Commercial
I
I
V
in Shutdown Mode
Power Supply Current V = 3.0V
BATT
CY2291/CY2291F
50
15
μA
μA
DDS
DD
excluding V
BATT
V
BATT
BATT
Notes
5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at V /2.
DD
7. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended
that a 150Ω pull up resistor to V be connected to the Xout pin.
DD
9. Xtal inputs have CMOS thresholds.
10. Load = Max., V = 0V or V , Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations vary. Power can be approximated by the following formula
IN
DD
(multiply by 0.65 for 3V operation): I =10+0.06•(F
DD
+F
+2•F
)+0.27•(F
+F
+F
+F
+F
+F
+F
).
CPLL UPLL
SPLL
CLKA
CLKB CLKC
CLKD CPUCLK CLKF XBUF
Document #: 38-07189 Rev. *C
Page 4 of 12
CY2291
Electrical Characteristics, Commercial 3.3V
Parameter
Description
HIGH-Level Output Voltage I = 4.0 mA
Conditions
Min.
Typ.
Max.
Unit
V
V
2.4
OH
OH
V
V
LOW-Level Output Voltage
I
I
= 4.0 mA
= 0.5 mA
0.4
V
OL
OL
32.768-kHz HIGH-Level
Output Voltage
V
0.5
V
OH–32
OH
BATT
V
32.768-kHz LOW-Level
Output Voltage
I
= 0.5 mA
0.4
V
OL–32
OL
V
V
I
Except crystal pins
Except crystal pins
2.0
V
V
HIGH-Level Input Voltage
IH
0.8
10
LOW-Level Input Voltage
Input HIGH Current
Input LOW Current
IL
V
V
= V –0.5V
<1
<1
μA
μA
μA
mA
IH
IN
DD
I
I
I
= +0.5V
10
IL
IN
Output Leakage Current
Three-state outputs
= V Max., 3.3V operation
250
65
OZ
DD
V
50
10
5
V
Supply Current
DD
DD
DD
Commercial
I
I
V
in Shutdown Mode
Power Supply Current V = 3.0V
BATT
CY2291/CY2291F
50
15
μA
μA
DDS
DD
excluding V
BATT
V
BATT
BATT
Electrical Characteristics, Industrial 5.0V
Parameter
Description
HIGH-Level Output Voltage I = 4.0 mA
Conditions
Min.
Typ.
Max.
Unit
V
V
2.4
OH
OH
V
V
LOW-Level Output Voltage
I
I
= 4.0 mA
= 0.5 mA
0.4
V
OL
OL
32.768-kHz HIGH-Level
Output Voltage
V
0.5
V
OH–32
OH
BATT
V
32.768-kHz LOW-Level
Output Voltage
I
= 0.5 mA
0.4
V
OL–32
OL
V
V
I
Except crystal pins
Except crystal pins
2.0
V
V
HIGH-Level Input Voltage
IH
0.8
10
LOW-Level Input Voltage
Input HIGH Current
Input LOW Current
IL
V
V
= V –0.5V
< 1
< 1
μA
μA
μA
mA
IH
IN
DD
I
I
I
= +0.5V
10
IL
IN
Output Leakage Current
Three-state outputs
= V Max., 5V operation
250
110
OZ
DD
V
75
10
5
V
Supply Current
DD
DD
DD
Industrial
I
I
V
in Shutdown Mode
Power Supply Current V = 3.0V
BATT
CY2291I/CY2291FI
100
15
μA
μA
DDS
DD
excluding V
BATT
V
BATT
BATT
Electrical Characteristics, Industrial 3.3V
Parameter
Description
HIGH-Level Output Voltage I = 4.0 mA
Conditions
Min.
Typ.
Max.
Unit
V
V
2.4
OH
OH
V
V
LOW-Level Output Voltage
I
I
= 4.0 mA
= 0.5 mA
0.4
V
OL
OL
32.768-kHz HIGH-Level
Output Voltage
V
0.5
V
OH–32
OH
BATT
V
32.768-kHz LOW-Level
Output Voltage
I
= 0.5 mA
0.4
V
OL–32
OL
Document #: 38-07189 Rev. *C
Page 5 of 12
CY2291
Electrical Characteristics, Industrial 3.3V (continued)
Parameter
Description
Conditions
Except crystal pins
Except crystal pins
Min.
Typ.
Max.
Unit
V
V
2.0
HIGH-Level Input Voltage
IH
IL
V
I
0.8
10
V
LOW-Level Input Voltage
Input HIGH Current
Input LOW Current
V
V
= V –0.5V
< 1
< 1
μA
μA
μA
mA
IH
IN
DD
I
I
I
= +0.5V
10
IL
IN
Output Leakage Current
Three-state outputs
= V max., 3.3V operation
250
70
OZ
DD
V
50
10
5
V
Supply Current
DD
DD
DD
Industrial
I
I
V
CY2291I/CY2291FI
100
15
μA
μA
DDS
DD
in Shutdown Mode
Power Supply Current V = 3.0V
BATT
excluding V
BATT
V
BATT
BATT
Switching Characteristics, Commercial 5.0V
Parameter
Name
Description
CY2291
Min.
Typ.
Max.
13000
(76.923 kHz)
Unit
t
Output Period Clock output range, 5V
operation
10
ns
1
(100 MHz)
CY2291F
11.1
(90 MHz)
13000
(76.923 kHz)
ns
Cycle
40%
45%
50%
50%
60%
55%
Duty cycle for outputs, defined as t ÷ t
OUT
2
1
f
> 66 MHZ
Duty cycle for outputs, defined as t ÷ t
2
1
f
< 66 MHZ
OUT
t
t
t
Rise Time
Fall Time
3
5
4
ns
ns
ns
Output clock rise time
3
4
5
2.5
10
Output clock fall time
Output Disable Time for output to enter three-state mode after
Time SHUTDOWN/OE goes LOW
15
t
t
t
t
t
t
t
t
Output Enable Time for output to leave three-state mode after
10
15
0.5
20.0
1
ns
ns
6
Time
SHUTDOWN/OE goes HIGH
[3,
Skew
< 0.25
Skew delay between any identical or related outputs
7
CPUCLK Slew Frequency transition rate
1.0
MHz/m
s
8
Peak-to-peak period jitter (t Max. – t min.),% of
< 0.5
< 0.7
< 400
< 250
< 25
%
ns
ps
ps
ms
Clock Jitter
Clock Jitter
Clock Jitter
Clock Jitter
9A
9B
9C
9D
10A
9A
9A
clock period (f
< 4 MHz)
OUT
Peak-to-peak period jitter (t Max. – t min.)
1
9B
9B
(4 MHz < f
< 16 MHz)
OUT
Peak-to-peak period jitter
(16 MHz < f < 50 MHz)
500
350
50
OUT
Peak-to-peak period jitter
(f > 50 MHz)
OUT
Lock Time for
CPLL
Lock Time from Power Up
Notes
11. XBUF duty cycle depends on XTALIN duty cycle.
12. Measured at 1.4V.
13. Measured between 0.4V and 2.4V.
14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application
note: “Jitter in PLL-Based Systems.”
15. CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL.
Document #: 38-07189 Rev. *C
Page 6 of 12
CY2291
Switching Characteristics, Commercial 5.0V (continued)
Parameter
Name
Description
Lock Time from Power Up
Min.
Typ.
Max.
Unit
t
Lock Time for
< 0.25
1
ms
10B
UPLL and SPLL
Slew Limits
CPU PLL Slew Limits
CY2291
8
8
100
90
MHz
MHz
CY2291F
Switching Characteristics, Commercial 3.3V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t
Output Period Clock output range, 3.3V
operation
CY2291
12.5
(80 MHz)
13000
(76.923 kHz)
ns
1
CY2291F
15
13000
(76.923 kHz)
ns
(66.6 MHz)
Cycle
40%
45%
50%
50%
60%
55%
Duty cycle for outputs, defined as t ÷ t
OUT
2
1
f
> 66 MHZ
Duty cycle for outputs, defined as t ÷ t
2
1
f
< 66 MHZ
OUT
t
t
t
Rise Time
Fall Time
3
5
4
ns
ns
ns
Output clock rise time
3
4
5
2.5
10
Output clock fall time
Output Disable Time for output to enter three-state mode after
Time SHUTDOWN/OE goes LOW
15
t
t
t
t
t
t
t
t
t
Output Enable Time for output to leave three-state mode after
10
15
0.5
20.0
1
ns
ns
6
Time
SHUTDOWN/OE goes HIGH
[3,
Skew
< 0.25
Skew delay between any identical or related outputs
7
CPUCLK Slew Frequency transition rate
1.0
MHz/m
s
8
Peak-to-peak period jitter (t Max. – t min.),% of
<0.5
<0.7
<400
<250
<25
%
ns
ps
Clock Jitter
Clock Jitter
Clock Jitter
Clock Jitter
9A
9B
9C
9D
10A
10B
9A
9A
clock period (f
< 4 MHz)
OUT
Peak-to-peak period jitter (t Max. – t min.) (4 MHz
1
9B
9B
< f
< 16 MHz)
OUT
Peak-to-peak period jitter
(16 MHz < f < 50 MHz)
500
350
50
1
OUT
Peak-to-peak period jitter
(f > 50 MHz)
ps
OUT
Lock Time for
CPLL
Lock Time from Power Up
Lock Time from Power Up
CPU PLL Slew Limits
ms
ms
Lock Time for
UPLL and SPLL
<0.25
Slew Limits
CY2291
CY2291F
8
8
80
MHz
MHz
66.6
Document #: 38-07189 Rev. *C
Page 7 of 12
CY2291
Switching Characteristics, Industrial 5.0V
Parameter
Name
Description
CY2291I
Min.
Typ.
Max.
Unit
t
Output Period Clock output range,
5V operation
11.1
(90 MHz)
13000
(76.923 kHz)
ns
1
CY2291FI
12.5
(80 MHz)
13000
(76.923 kHz)
ns
40%
45%
50%
50%
60%
55%
Cycle
Duty cycle for outputs, defined as t ÷ t
OUT
2
1
1
f
> 66 MHZ
Duty cycle for outputs, defined as t ÷ t
2
f
< 66 MHZ
OUT
t
t
t
3
5
4
ns
ns
ns
Rise Time
Fall Time
Output clock rise time
3
4
5
2.5
10
Output clock fall time
Output Disable Time for output to enter three-state mode after
Time SHUTDOWN/OE goes LOW
15
t
t
t
t
t
t
t
t
t
Output Enable Time for output to leave three-state mode after
10
15
0.5
20.0
1
ns
ns
6
Time
SHUTDOWN/OE goes HIGH
[3,
Skew
< 0.25
Skew delay between any identical or related outputs
7
CPUCLK Slew Frequency transition rate
1.0
MHz/m
s
8
Peak-to-peak period jitter (t Max. – t min.),% of
<0.5
<0.7
<400
<250
<25
%
ns
ps
Clock Jitter
Clock Jitter
Clock Jitter
Clock Jitter
9A
9B
9C
9D
10A
10B
9A
9A
clock period (f
< 4 MHz)
OUT
Peak-to-peak period jitter (t Max. – t min.) (4 MHz
1
9B
9B
< f
< 16 MHz)
OUT
Peak-to-peak period jitter
(16 MHz < f < 50 MHz)
500
350
50
1
OUT
Peak-to-peak period jitter
(f > 50 MHz)
ps
OUT
Lock Time for
CPLL
Lock Time from Power Up
Lock Time from Power Up
CPU PLL Slew Limits
ms
ms
Lock Time for
UPLL and SPLL
<0.25
Slew Limits
CY2291I
CY2291FI
8
8
90
80
MHz
MHz
Switching Characteristics, Industrial 3.3V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t
Output Period Clock output range, 3.3V
operation
CY2291I
15
13000
(76.923 kHz)
ns
1
(66.6 MHz)
CY2291FI
16.66
(60 MHz)
13000
(76.923 kHz)
ns
Cycle
40%
45%
50%
50%
60%
55%
Duty cycle for outputs, defined as t ÷ t
OUT
2
1
1
f
> 66 MHZ
Duty cycle for outputs, defined as t ÷ t
2
f
< 66 MHZ
OUT
t
t
t
Rise Time
Fall Time
3
5
4
ns
ns
ns
Output clock rise time
3
4
5
2.5
10
Output clock fall time
Output Disable Time for output to enter three-state mode after
Time SHUTDOWN/OE goes LOW
15
Document #: 38-07189 Rev. *C
Page 8 of 12
CY2291
Switching Characteristics, Industrial 3.3V (continued)
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t
Output Enable Time for output to leave three-state mode after
10
15
ns
6
Time
SHUTDOWN/OE goes HIGH
[3,
t
Skew
< 0.25
0.5
ns
Skew delay between any identical or related outputs
7
t
t
CPUCLK Slew Frequency transition rate
1.0
20.0
1
MHz/ms
%
8
Peak-to-peak period jitter (t Max. – t min.),% of
< 0.5
< 0.7
< 400
Clock Jitter
Clock Jitter
Clock Jitter
Clock Jitter
9A
9A
9A
clock period (f
< 4 MHz)
OUT
t
t
Peak-to-peak period jitter (t Max. – t min.) (4 MHz
1
ns
ps
9B
9C
9B
9B
< f
< 16 MHz)
OUT
Peak-to-peak period jitter
(16 MHz < f < 50 MHz)
500
OUT
t
t
Peak-to-peak period jitter (f
Lock Time from Power Up
> 50 MHz)
< 250
< 25
350
50
ps
9D
OUT
Lock Time for
CPLL
ms
10A
t
Lock Time for
UPLL and SPLL
Lock Time from Power Up
CPU PLL Slew Limits
< 0.25
1
ms
10B
Slew Limits
CY2291I
8
8
66.6
60
MHz
MHz
CY2291FI
Switching Waveforms
Figure 2. All Outputs, Duty Cycle and Rise/Fall Time
t
1
t
2
OUTPUT
t
3
t
4
Figure 3. Output Three-State Timing
OE
t
5
t
6
ALL
THREE-STATE
OUTPUTS
Figure 4. CLK Outputs Jitter and Skew
t
9A
CLK
OUTPUT
t7
RELATED
CLK
Document #: 38-07189 Rev. *C
Page 9 of 12
CY2291
Switching Waveforms
Figure 5. CPU Frequency Change
OLD SELECT
NEW SELECT STABLE
t & t
SELECT
F
new
F
old
8
10
CPU
Test Circuit
VDD
CLK out
CLOAD
0.1 μF
0.1 μF
OUTPUTS
VDD
GND
Ordering Information
Ordering Code
Package Type
Operating Range
Operating Voltage
20-Pin SOIC
20-Pin SOIC
Industrial
3.3V or 5.0V
CY2291FI
Pb-Free
CY2291SXC–XXX
CY2291SXC–XXXT
CY2291SXL–XXX
CY2291SXL–XXXT
CY2291FX
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
5.0V
20-Pin SOIC – Tape and Reel
20-Pin SOIC
5.0V
3.3V
20-Pin SOIC – Tape and Reel
20-Pin SOIC
3.3V
3.3V or 5.0V
3.3V or 5.0V
CY2291FXT
20-Pin SOIC – Tape and Reel
Package Characteristics
Package
θ
(C/W)
θ
(C/W)
Transistor Count
JA
JC
20-pin SOIC
125
25
9271
Note
16. Not recommended for new designs.
Document #: 38-07189 Rev. *C
Page 10 of 12
CY2291
Package Diagram
Figure 6. 20-Pin (300 MIL) SOIC Package Outline
51-85024 *C
Document #: 38-07189 Rev. *C
Page 11 of 12
CY2291
Document History Page
Document Title: CY2291 Three-PLL General Purpose EPROM Programmable Clock Generator
Document Number: 38-07189
Orig. of Submission
REV.
ECN
Description of Change
Change
Date
**
110321
121836
276756
SZV
10/28/01
12/14/02
10/18/04
09/16/08
Change from Spec number: 38-00410 to 38-07189
*A
*B
*C
RBI
Power up requirements added to Operating Conditions Information
Added Lead Free Devices
RGL
2565316 AESA/KVM
Updated template. Added Note “Not recommended for new designs.”
Removed part number CY2291F, CY2291FT, CY2291SC-XXX,
CY2291SC-XXXT, CY2291SI-XXX, CY2291SI-XXXT, CY2291SL-XXX,
CY2291SL-XXXT, CY2291FIT, CY2291SXI-XXX, CY2291SXI-XXXT,
CY2291FXI and CY2291FXIT. Changed CyClocks reference to include
CyberClocks. Changed Lead-Free to Pb-Free.
Updated Package diagram 51-85024 *B to 51-85024 *C.
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© Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07189 Rev. *C
Revised September 16, 2008
Page 12 of 12
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of their respective holders.
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